7.2 A Highly Versatile 0.18um CMOS Technology With Dense Embedded SRAM

We report on a 3.3V12.5V compatible, 1.5V high performance dense CMOS SRAM technology utilizing a 2.74 um2 6-T Bitcell. This 0.18pm CMOS process with a nominal 0.13pm gate poly and a 30A gate oxide utilizes aggressive interwell isolation, enhanced self-aligned local interconnect, low-K interlevel dielectric, and scaled copper metalization. In addition, the technology allows for low leakage, high density and SER resistant Embedded SRAM applications by allowing integration of low leakage array transistors, Buried Channel PMOS loads, self-aligned contacts and Triple Well in the memory array. Finally, this integration includes a 70&30A DGO technology for 3.3V interfaces. High performance 6-T bitcell operation, 8h4b stand-alone SRAM yield and high performance DSP circuit with 4Mb embedded memory with this aggressively scaled bitcell has been successfully demonstrated. Cell currents of 85pA has been achieved for a supply voltage of 1.5V while maintaining static noise margin in excess of 220mV INTRODUCTION High performance workstation and server systems require ultra-fast SRAM chips with high density, low power, fast clock rate and low cost. The logic based SRAM technology described in this work is suitable for stand-alone as well as embedded system applications. The 6-T transistor CMOS SRAM technology utilizes 0.131t0.02 pm gate length, 30A gate oxide periphery and array transistors based on shallow trench isolation, retrograde well, CO salicide, and dual in-laid copper metalization fiom the technology platform [l]. To realize the unique requirements of scaled cell area, stable and high speed cell operation for SRAM array [2-31, process enhancement such as aggressive active spacing of 0.2 1 pm and n+ to p+ isolation down to 0.42pm, capped gate array transistors with low leakage current, 0.18pm self-aligned local interconnect, and low K interlevel dielectric film has been developed. In order to realize the three different flavors of transistors namely, (i) 30A high performance, (ii) 30A low leakage with triple well and (iii) 70A 3.3V VO, significant integration and implant optimization was involved. Table 1 shows the salient technology features and in the following sections, we discuss the process integration steps required to achieve these electrical characteristics. The SRAM process is based on a high performance core CMOS platform technology in which SRAM serves as an enhanced add-on module. Figs. 1-2 show SRAM cell array crosssection and the cell layout, respectively. For scaled SRAM cell area requirement, active spacing of 0.21 pm and n+ to p+ spacing down to 0.42 pm with a triple well option have been achieved with optimized photo and implant conditions (Fig. 3). Surface channel nMOS and buried channel PMOS transistors with dielectric capped gate and low leakage current characteristics are used to enable the formation of self-aligned local interconnect in which gate poly features are electrically isolated fiom the local interconnect. Extensive optical proximity correction (OPC) has been utilized in the mask layout (as shown in Fig. 2) for critical levels and an anti-reflect film is used in the dielectric stack to optimize the photo printing characteristics for gate and local interconnect layers. The self-aligned local interconnect is defined by selectively etching the in-laid features as small as 0.lSpm with respect to an etch stop layer. DGO transistors with 70A gate PROCESS INTEGRATION 166 o-78o3-63o~-4/oo~$io.oo 2000 IEEE oxide are also integrated for 3.312.5V U 0 operations. For enhanced SRAM speed operation, a low-K interlevel dielectric film with a dielectric constant of 3.5 (vs. 4.1 for conventional TEOS ILD layers) is used. The process is completed using a 5level scaled in-laid Cu metalization. ELECTRICAL RESULTS As is clear fiom the versatility of this integration, 3 different sets on Nand P-FETs have to be optimized. Fig. 4 shows the sequence of process steps required to achieve the different transistor targets without compromising the performance of any. Since the scaling of BCPFET is the most challenging, careful optimization of the BCPFET channel is done by increasing both boron and retrograde well (antimony) doses. A narrow width and high concentration counterdoped layer which is unaffected by the DGO heat is realized and excellent Vt roll-off is achieved (Fig. 5). As seen fiom Fig. 4 only two additional reticles are used for the DGO integration in order to keep the process cost effective. This implies the channel implants cannot be optimized separately for both transistors, therefore making simultaneous Vt targeting for 30A core and 70A VO transistors a difficult task. Channel dopant segregation during DGO heat poses an additional challenge. A low doped channel in conjunction with heavy halo approach is used to get around the problem of Vt lowering during DGO process as shown in Fig. 6. Fig. 7 shows leakage current distribution fiom self-aligned local interconnect and self-aligned contact array test structures. While maintaining low leakage SAL1 and SAC characteristics for the SRAM array, a low metal-11-active contact resistance is achieved (Fig. 8) which is critical for a low bitline parasitic. The low-K ILD layer used in the process can further reduce parasitic capacitance by 14% as compared with conventional TEOS ILD, thus improving circuit speed performance. Fig. 9 shows in-laid Cu interconnect sheet resistance for metal 1 to metal 5. The minimum metal length is scaled to 0.28pm and the minimum contadvia sizes are 0.25pm10.315 pm, respectively for this technology generation. Fig. 10 shows the SRAM cell transfer characteristics and cell current. A cell current of 85pA has been achieved for a supply voltage of 1.5V while maintaining the static noise margin in excess of 220mV. The SRAM array transistors use a cell ratio of 1.25 with drive W L of 0.23pm10.13pm. As mentioned before, the overall bitcell leakage is -1pA at room teperature. This is achieved with low leakage BCPFET loads and low leakage latch gates. Fig. 11 shows bitcell leakage and the various components of leakage in the bitcell over temperature. A high performance 1.5V CMOS Embedded SRAM technology has been developed and demonstrated on a 2.74pm2 cell area using aggressive interwell isolation, self-aligned local interconnect, low-K ILD layer, and scaled in-laid Cu metallization. A cell current of 85pA and a static noise margin of 220mV at 1.5V have been achieved. CONCLUSIONS ACKNOWLEDGMENTS The authors acknowledge the support fiom the Design Group, APRDL process engineering and pilot line. Management support fiom Bob Yeargain and Fabio Pintchovski is appreciated. [l] P. Gilbert et al., IEDM 1998, p [2] M. Woo et al., VLSI 1998, p.12 [3] C. Lage et al., IEDM 1996, p. 271 REFERENCES 2000 Symposium on VLSl Technology Digest of Technical Papers Fig.1 SEM cross-section of SRAM cell array using self-aligned local interconnect and scaled in-laid Cu metallization. ,, 30A oxide grow ,, Gate patterning ,, Corelhigh-Vt NPFET LDD 4, DGO NFET MDD -DGO mask 2